module testbench;

reg clk;
reg reset;
reg error;

!highlight!reg t_sim;

initial begin
  clk = 0;
  forever #5 clk = ~clk;
end

initial begin
  reset = 1;
  #35 
  reset = 0;
  #25
  reset = 1;
end

initial begin
  error = 1;
  #20 
  error = 0;
  #100
  error = 1;
end

initial begin
  $dumpfile("wave.vcd");
  $dumpvars;
end

initial begin
  t_sim = 0;
  #200 t_sim = 1;
!highlight!  $finish;
end

endmodule